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- Using the BUFIO makes another clock domain....FPGAs apparently hate clock domain crossings, avoid them at all cost. - Now moving back to having on high speed clock domain for logic and DDR blocks, take care of IO alignment in software for TX and RX - Also, fixed the io_wait path with logic...not sure what I was thinking there. Logic was trivial. The way it was,the io path was going straight into the FIFO as a wait.
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OH!
An Open Hardware Library for Chip and FPGA designers written in Verilog
CONTENT
| Spec | Description |
|---|---|
| common | Common utility modules and scripts |
| edma | DMA module |
| emesh | Epiphany emesh related circuits |
| elink | Epiphany point to point LVDS link |
| emailbox | Simple mailbox with interrupt output |
| emmu | Simple memory transaction translation unit |
| memory | Various simple memory structures (RAM/FIFO) |
| xilibs | Simulation modules for Xilinx primitives |
LICENSE
The OH! repository source code is licensed under the MIT license unless otherwise specified. See LICENSE for full copyright terms.
CONTRIBUTING
Instructions for contributing can be found HERE.