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18 lines
350 B
Verilog
18 lines
350 B
Verilog
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module IBUF_IBUFDISABLE (O, I, IBUFDISABLE);
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parameter IBUF_LOW_PWR = "TRUE";
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parameter IOSTANDARD = "DEFAULT";
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parameter SIM_DEVICE = "7SERIES";
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parameter USE_IBUFDISABLE = "TRUE";
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`ifdef XIL_TIMING
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parameter LOC = "UNPLACED";
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`endif // `ifdef XIL_TIMING
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output O;
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input I;
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input IBUFDISABLE;
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endmodule
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