mirror of
https://github.com/aolofsson/oh.git
synced 2025-02-07 06:44:09 +08:00
26 lines
335 B
Verilog
26 lines
335 B
Verilog
/*Differential output buffer primitive
|
|
*
|
|
*
|
|
*/
|
|
|
|
module OBUFDS (/*AUTOARG*/
|
|
// Outputs
|
|
O, OB,
|
|
// Inputs
|
|
I
|
|
);
|
|
|
|
parameter CAPACITANCE = "DONT_CARE";
|
|
parameter IOSTANDARD = "DEFAULT";
|
|
parameter SLEW = "SLOW";
|
|
|
|
input I;
|
|
output O, OB;
|
|
|
|
|
|
assign O = I;
|
|
assign OB = ~I;
|
|
|
|
endmodule // OBUFDS
|
|
|