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16 lines
286 B
Verilog
16 lines
286 B
Verilog
module OBUFDS_GTE3_ADV #(
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`ifdef XIL_TIMING //Simprim
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parameter LOC = "UNPLACED",
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`endif
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parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
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parameter [4:0] REFCLK_ICNTL_TX = 5'b00000
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)(
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output O,
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output OB,
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input CEB,
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input [3:0] I,
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input [1:0] RXRECCLK_SEL
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);
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endmodule
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