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394920a1e7
- As a dirty a model hack as they come, using positive and negative edge of CLKIN to sample the signal and phase align the clock output. - Will only work with div 2/4/8 etc - There may be other issues, have to think about it... - But the test now passes cleanly and the clocks look good.
This folder contains basic Xilinx verilog primitives
All primitives should be written in "synthesizable" code that can be simulated in Verilator and which should work correctly when synthesized.