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28 lines
364 B
Verilog
28 lines
364 B
Verilog
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module toggle2pulse(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in, reset
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);
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//clocks
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input clk;
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input in;
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output out;
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//reset
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input reset;
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reg out_reg;
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always @ (posedge clk)
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if(reset)
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out_reg <= 1'b0;
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else
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out_reg <= in;
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assign out = in ^ out_reg;
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endmodule
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