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141 lines
4.6 KiB
Verilog
141 lines
4.6 KiB
Verilog
module erx_fifo (/*AUTOARG*/
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// Outputs
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rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
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rxrr_packet, rxrd_fifo_wait, rxrr_fifo_wait, rxwr_fifo_wait,
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// Inputs
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erx_reset, sys_reset, rx_lclk_div4, sys_clk, rxwr_wait, rxrd_wait,
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rxrr_wait, rxrd_fifo_access, rxrd_fifo_packet, rxrr_fifo_access,
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rxrr_fifo_packet, rxwr_fifo_access, rxwr_fifo_packet
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h800;
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//reset & clocks
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input erx_reset;
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input sys_reset;
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input rx_lclk_div4;
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input sys_clk;
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//WR to AXI master
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output rxwr_access;
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output [PW-1:0] rxwr_packet;
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input rxwr_wait;
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//RD to AXI master
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output rxrd_access;
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output [PW-1:0] rxrd_packet;
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input rxrd_wait;
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//RR to AXI slave
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output rxrr_access;
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output [PW-1:0] rxrr_packet;
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input rxrr_wait;
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//RD from IO
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input rxrd_fifo_access; // To rxrd_fifo of fifo_cdc.v
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input [PW-1:0] rxrd_fifo_packet; // To rxrd_fifo of fifo_cdc.v
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output rxrd_fifo_wait; // From rxrd_fifo of fifo_cdc.v
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//RR from IO
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input rxrr_fifo_access; // To rxrr_fifo of fifo_cdc.v
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input [PW-1:0] rxrr_fifo_packet; // To rxrr_fifo of fifo_cdc.v
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output rxrr_fifo_wait; // From rxrr_fifo of fifo_cdc.v
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//WR from IO
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input rxwr_fifo_access; // To rxwr_fifo of fifo_cdc.v
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input [PW-1:0] rxwr_fifo_packet; // To rxwr_fifo of fifo_cdc.v
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output rxwr_fifo_wait; // From rxwr_fifo of fifo_cdc.v
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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/************************************************************/
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/*FIFOs */
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/*(for AXI 1. read request, 2. write, and 3. read response) */
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/************************************************************/
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/*fifo_cdc AUTO_TEMPLATE (
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// Outputs
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.packet_out (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
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.access_out (@"(substring vl-cell-name 0 4)"_access),
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.wait_out (@"(substring vl-cell-name 0 4)"_fifo_wait),
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// Inputs
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.clk_out (sys_clk),
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.clk_in (rx_lclk_div4),
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.access_in (@"(substring vl-cell-name 0 4)"_fifo_access),
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.wait_in (@"(substring vl-cell-name 0 4)"_wait),
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.reset_in (erx_reset),
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.reset_out (sys_reset),
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.packet_in (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
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);
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*/
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//Read request fifo (from Epiphany)
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fifo_cdc #(.DW(104), .DEPTH(32))
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rxrd_fifo (
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/*AUTOINST*/
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// Outputs
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.wait_out (rxrd_fifo_wait), // Templated
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.access_out (rxrd_access), // Templated
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.packet_out (rxrd_packet[PW-1:0]), // Templated
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// Inputs
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.clk_in (rx_lclk_div4), // Templated
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.reset_in (erx_reset), // Templated
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.access_in (rxrd_fifo_access), // Templated
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.packet_in (rxrd_fifo_packet[PW-1:0]), // Templated
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.clk_out (sys_clk), // Templated
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.reset_out (sys_reset), // Templated
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.wait_in (rxrd_wait)); // Templated
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//Write fifo (from Epiphany)
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fifo_cdc #(.DW(104), .DEPTH(32))
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rxwr_fifo(
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/*AUTOINST*/
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// Outputs
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.wait_out (rxwr_fifo_wait), // Templated
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.access_out (rxwr_access), // Templated
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.packet_out (rxwr_packet[PW-1:0]), // Templated
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// Inputs
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.clk_in (rx_lclk_div4), // Templated
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.reset_in (erx_reset), // Templated
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.access_in (rxwr_fifo_access), // Templated
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.packet_in (rxwr_fifo_packet[PW-1:0]), // Templated
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.clk_out (sys_clk), // Templated
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.reset_out (sys_reset), // Templated
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.wait_in (rxwr_wait)); // Templated
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//Read response fifo (for host)
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fifo_cdc #(.DW(104), .DEPTH(32))
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rxrr_fifo(
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/*AUTOINST*/
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// Outputs
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.wait_out (rxrr_fifo_wait), // Templated
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.access_out (rxrr_access), // Templated
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.packet_out (rxrr_packet[PW-1:0]), // Templated
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// Inputs
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.clk_in (rx_lclk_div4), // Templated
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.reset_in (erx_reset), // Templated
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.access_in (rxrr_fifo_access), // Templated
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.packet_in (rxrr_fifo_packet[PW-1:0]), // Templated
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.clk_out (sys_clk), // Templated
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.reset_out (sys_reset), // Templated
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.wait_in (rxrr_wait)); // Templated
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endmodule // erx
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
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// End:
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