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27 lines
383 B
Verilog
27 lines
383 B
Verilog
module oh_bitreverse (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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parameter DW = 64; // width operation
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input [DW-1:0] in; // data input
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output [DW-1:0] out; // bit reversed output
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reg [DW-1:0] out;
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integer i;
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always @*
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for (i=0;i<DW;i=i+1)
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out[i]=in[DW-1-i];
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endmodule // oh_bitreverse
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