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119 lines
3.0 KiB
Verilog
119 lines
3.0 KiB
Verilog
//#############################################################################
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//# Function: GPIO Pads #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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//#
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//# IO BUFFER CONFIG
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//# 0 = pull_enable (1=enable)
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//# 1 = pull_select (1=pull up)
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//# 2 = slew limiter
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//# 3 = shmitt trigger enable
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//# 4 = ds[0]
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//# 5 = ds[1]
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//# 6 = ds[2]
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//# 7 = ds[3]
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//#
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//#############################################################################
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module oh_pads_gpio
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#(parameter NGPIO = 8, // total IO signal pads
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parameter NVDDIO = 8, // total IO supply pads
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parameter NVSSIO = 8, // total IO ground pads
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parameter DIR = "NO" // "NO", "SO", "EA", "WE"
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)
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(//pad
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inout [NGPIO-1:0] pad, // pad
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//feed through signals
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inout vddio, // io supply
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inout vssio, // io ground
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inout vdd, // core supply
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inout vss, // common ground
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inout poc, // power-on-ctrl
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//core facing signals
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input [NGPIO-1:0] dout, // data to drive to pad
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output [NGPIO-1:0] din, // data from pad
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input [NGPIO-1:0] oen, // output enable (bar)
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input [NGPIO-1:0] ie, // input enable
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input [NGPIO*8-1:0] cfg // io config
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);
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//########################################################
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//# GPIO PINS
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//########################################################
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genvar i;
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generate
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for(i=0;i<NGPIO;i=i+1)
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begin : g00
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`ifdef CFG_ASIC
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asic_iobuf #(.DIR(DIR))
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dpad (// Outputs
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.out (din[i]),
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// Inouts
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.poc (poc),
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.vdd (vdd),
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.vss (vss),
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.vddio (vddio),
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.vssio (vssio),
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.pad (pad[i]),
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// Inputs
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.pe (cfg[8*i]),
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.ie (ie[i]),
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.i (dout[i]),
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.oen (oen[i]),
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.ps (cfg[8*i+1]),
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.sl (cfg[8*i+2]),
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.ds (cfg[(8*i+4)+:4]));
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`else
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assign din[i] = pad[i] & ie[i];
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assign pad[i] = ~oen ? dout[i] : 1'bz;
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`endif
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end
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endgenerate
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//########################################################
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//# IO SUPPLY PINS
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//########################################################
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`ifdef CFG_ASIC
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generate
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for(i=0;i<NVDDIO;i=i+1)
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begin : g10
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//VDDIO
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asic_iosupply #(.DIR(DIR))
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ivddio (.vdd (vdd),
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.vss (vss),
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.vddio (vddio),
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.vssio (vssio),
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.poc (poc));
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end
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endgenerate
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`endif
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//########################################################
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//# IO GROUND PINS
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//########################################################
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`ifdef CFG_ASIC
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generate
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for(i=0;i<NVSSIO;i=i+1)
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begin : g10
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//VSSIO
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asic_ioground #(.DIR(DIR))
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ivssio (.vdd (vdd),
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.vss (vss),
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.vddio (vddio),
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.vssio (vssio),
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.poc (poc));
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end
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endgenerate
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`endif
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endmodule // io_pads_gpio
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// Local Variables:
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// verilog-library-directories:("." )
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// End:
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