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oh/stdlib
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aolofsson 3ad1b03fe7 Removing dut feedback loop from simulation control 
- ...to complicated...
- incloding a simple linear test flow for "80%" of foofoo testing
-
2022-06-27 00:22:02 -04:00
..
firmware
Flattening directory tree (again)
2022-06-21 14:48:48 -04:00
fpga
Flattening directory tree (again)
2022-06-21 14:48:48 -04:00
rtl
Making stimulus memory a portable RAM
2022-06-24 22:41:52 -04:00
testbench
Removing dut feedback loop from simulation control
2022-06-27 00:22:02 -04:00
README.md
Flattening directory tree (again)
2022-06-21 14:48:48 -04:00

README.md

STDLIB

  • STDLIB is a library of low level vectoried building blocks for control and datapath logic.
  • Where appropriate, parameters are included to enable soft and hard-coded implementation.
  • Some library cells call on others cells within the library