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oh/asiclib/hdl/asic_and3.v
aolofsson 9e41b55f22 Adding default property to all cells
-Can be used to select between different cells (like sizes) that have the exact same logical function
2021-07-27 22:55:45 -04:00

17 lines
545 B
Verilog

//#############################################################################
//# Function: 3-Input And Gate #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module asic_and3 #(parameter PROP = "DEFAULT") (
input a,
input b,
input c,
output z
);
assign z = a & b & c;
endmodule