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9e41b55f22
-Can be used to select between different cells (like sizes) that have the exact same logical function
23 lines
727 B
Verilog
23 lines
727 B
Verilog
//#############################################################################
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//# Function: Integrated "Or" Clock Gating Cell #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_clkicgor #(parameter PROP = "DEFAULT") (
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input clk,// clock input
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input te, // test enable
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input en, // enable
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output eclk // enabled clock output
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);
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reg en_stable;
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always @ (clk or en or te)
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if (clk)
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en_stable <= en | te;
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assign eclk = clk | ~en_stable;
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endmodule
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