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20 lines
628 B
Verilog
20 lines
628 B
Verilog
//#############################################################################
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//# Function: Carry Save Adder (3:2) #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_csa32 #(parameter PROP = "DEFAULT")
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(
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input a,
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input b,
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input c,
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output sum,
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output carry
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);
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assign sum = a ^ b ^ c;
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assign carry = (a & b) | (b & c) | (c & a);
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endmodule
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