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9e41b55f22
-Can be used to select between different cells (like sizes) that have the exact same logical function
28 lines
922 B
Verilog
28 lines
922 B
Verilog
//#############################################################################
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//# Function: Dual data rate input buffer #
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//# Copyright: OH Project Authors. All rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_iddr #(parameter PROP = "DEFAULT") (
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input clk, // clock
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input in, // data input sampled on both edges of clock
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output reg outrise, // rising edge sample
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output reg outfall // falling edge sample
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);
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// Negedge Sample
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always @ (negedge clk)
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outfall <= in;
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// Posedge Sample
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reg inrise;
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always @ (posedge clk)
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inrise <= in;
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// Posedge Latch (for hold)
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always @ (clk or inrise)
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if(~clk)
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outrise <= inrise;
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endmodule
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