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-Can be used to select between different cells (like sizes) that have the exact same logical function
24 lines
787 B
Verilog
24 lines
787 B
Verilog
//#############################################################################
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//# Function: Dual data rate output buffer #
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//# Copyright: OH Project Authors. All rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_oddr #(parameter PROP = "DEFAULT") (
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input clk, // clock input
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input in0, // data for clk=0
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input in1, // data for clk=1
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output out // dual data rate output
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);
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//Making in1 stable for clk=1
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reg in1_sh;
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always @ (clk or in1)
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if(~clk)
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in1_sh <= in1;
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//Using clock as data selctor
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assign out = clk ? in1_sh : in0;
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endmodule
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