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9e41b55f22
-Can be used to select between different cells (like sizes) that have the exact same logical function
24 lines
777 B
Verilog
24 lines
777 B
Verilog
//#############################################################################
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//# Function: Positive edge-triggered static D-type flop-flop with async #
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//# active low preset and scan input. #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_sdffsq #(parameter PROP = "DEFAULT") (
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input d,
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input si,
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input se,
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input clk,
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input nset,
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output reg q
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);
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always @ (posedge clk or negedge nset)
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if(!nset)
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q <= 1'b1;
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else
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q <= se ? si : d;
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endmodule
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