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oh/asiclib/hdl/asic_aoi211.v
aolofsson 3dbb3755af Adding asiclib
-Represent set of cells that need hard coded cells or hard coded gate level designs.
2021-07-27 22:24:40 -04:00

19 lines
548 B
Verilog

//#############################################################################
//# Function: And-Or-Inverter (aoi211) Gate #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module asic_aoi211
(
input a0,
input a1,
input b0,
input c0,
output z
);
assign z = ~((a0 & a1) | b0 | c0);
endmodule