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19 lines
556 B
Verilog
19 lines
556 B
Verilog
//#############################################################################
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//# Function: And-Or-Inverter (aoi22) Gate #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_aoi22
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(
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input a0,
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input a1,
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input b0,
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input b1,
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output z
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);
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assign z = ~((a0 & a1) | (b0 & b1));
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endmodule
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