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24 lines
723 B
Verilog
24 lines
723 B
Verilog
//#############################################################################
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//# Function: Integrated "And" Clock Gating Cell (And) #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_clkicgand
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(
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input clk, // clock input
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input te, // test enable
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input en, // enable (from positive edge FF)
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output eclk // enabled clock output
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);
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reg en_stable;
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always @ (clk or en or te)
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if (~clk)
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en_stable <= en | te;
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assign eclk = clk & en_stable;
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endmodule
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