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24 lines
737 B
Verilog
24 lines
737 B
Verilog
//#############################################################################
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//# Function: Carry Save Adder (4:2) (aka 5:3) #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_csa42
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( input a,
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input b,
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input c,
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input d,
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input cin,
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output sum,
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output carry,
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output cout
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);
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assign cout = (a & b) | (b & c) | (a & c);
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assign sumint = a ^ b ^ c;
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assign sum = cin ^ d ^ sumint;
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assign carry = (cin & d) | (cin & sumint) | (d & sumint);
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endmodule
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