mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
18 lines
537 B
Verilog
18 lines
537 B
Verilog
//#############################################################################
|
|
//# Function: Negative edge-triggered static D-type flop-flop #
|
|
//# Copyright: OH Project Authors. ALl rights Reserved. #
|
|
//# License: MIT (see LICENSE file in OH repository) #
|
|
//#############################################################################
|
|
|
|
module asic_dffnq
|
|
(
|
|
input d,
|
|
input clk,
|
|
output reg q
|
|
);
|
|
|
|
always @ (negedge clk)
|
|
q <= d;
|
|
|
|
endmodule
|