mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
23 lines
710 B
Verilog
23 lines
710 B
Verilog
//#############################################################################
|
|
//# Function: Positive edge-triggered static inverting D-type flop-flop with #
|
|
// async active low reset. #
|
|
//# Copyright: OH Project Authors. ALl rights Reserved. #
|
|
//# License: MIT (see LICENSE file in OH repository) #
|
|
//#############################################################################
|
|
|
|
module asic_dffrqn
|
|
(
|
|
input d,
|
|
input clk,
|
|
input nreset,
|
|
output reg qn
|
|
);
|
|
|
|
always @ (posedge clk or negedge nreset)
|
|
if(!nreset)
|
|
qn <= 1'b1;
|
|
else
|
|
qn <= ~d;
|
|
|
|
endmodule
|