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3dbb3755af
-Represent set of cells that need hard coded cells or hard coded gate level designs.
19 lines
550 B
Verilog
19 lines
550 B
Verilog
//#############################################################################
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//# Function: D-type active-low transparent latch #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_latnq
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(
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input d,
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input clk,
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output reg q
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);
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always @ (clk or d)
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if(~clk)
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q <= d;
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endmodule
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