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25 lines
724 B
Verilog
25 lines
724 B
Verilog
//#############################################################################
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//# Function: 4-Input Inverting Mux #
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//# #
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//# Copyright: OH Project Authors. All rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_muxi4
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(
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input d0,
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input d1,
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input d2,
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input d3,
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input s0,
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input s1,
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output z
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);
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assign z = ~((d0 & ~s1 & ~s0) |
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(d1 & ~s1 & s0) |
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(d2 & s1 & ~s0) |
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(d2 & s1 & s0));
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endmodule
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