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26 lines
856 B
Verilog
26 lines
856 B
Verilog
//#############################################################################
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//# Function: Reset synchronizer #
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// (async assert, sync deassert) #
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//# Copyright: OH Project Authors. All rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_rsync
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(
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input clk,
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input nrst_in,
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output nrst_out
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);
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localparam SYNCPIPE=2;
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reg [SYNCPIPE-1:0] sync_pipe;
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always @ (posedge clk or negedge nrst_in)
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if(!nrst_in)
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sync_pipe[SYNCPIPE-1:0] <= 'b0;
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else
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sync_pipe[SYNCPIPE-1:0] <= {sync_pipe[SYNCPIPE-2:0],1'b1};
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assign nrst_out = sync_pipe[SYNCPIPE-1];
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endmodule
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