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26 lines
834 B
Verilog
26 lines
834 B
Verilog
//#############################################################################
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//# Function: Positive edge-triggered static D-type flop-flop with async #
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//# active low reset and scan input #
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//# #
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//# Copyright: OH Project Authors. All rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_sdffrq
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(
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input d,
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input si,
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input se,
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input clk,
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input nreset,
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output reg q
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);
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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q <= 1'b0;
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else
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q <= se ? si : d;
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endmodule
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