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25 lines
761 B
Verilog
25 lines
761 B
Verilog
//#############################################################################
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//# Function: Positive edge-triggered static inverting D-type flop-flop with #
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// async active low reset and scan input #
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//# Copyright: OH Project Authors. ALl rights Reserved. #
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//# License: MIT (see LICENSE file in OH repository) #
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//#############################################################################
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module asic_sdffrqn
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(
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input d,
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input si,
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input se,
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input clk,
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input nreset,
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output reg qn
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);
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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qn <= 1'b1;
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else
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qn <= se ? ~si : ~d;
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endmodule
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