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oh/asiclib/hdl/asic_xnor2.v
aolofsson 3dbb3755af Adding asiclib
-Represent set of cells that need hard coded cells or hard coded gate level designs.
2021-07-27 22:24:40 -04:00

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509 B
Verilog

//#############################################################################
//# Function: 2-Input Exclusive-Nor Gate #
//# Copyright: OH Project Authors. ALl rights Reserved. #
//# License: MIT (see LICENSE file in OH repository) #
//#############################################################################
module asic_xnor2
(
input a,
input b,
output z
);
assign z = ~(a ^ b);
endmodule