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63 lines
1.8 KiB
Verilog
63 lines
1.8 KiB
Verilog
// Standardized "DUT"
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module dut (/*AUTOARG*/
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// Outputs
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dut_active, access_out, packet_out, wait_out,
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// Inputs
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clk, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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parameter PW = 99;
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parameter N = 99;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active; //dut ready to go after reset
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//North side
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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input [N-1:0] wait_in;
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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output [N-1:0] wait_out;
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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//Drive dummy interface
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//This module should be replaced with actual device under test
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assign access_out ='b0;
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assign packet_out ='b0;
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assign wait_out ='b0;
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assign reset_done = 1'b1;
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endmodule // dut
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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