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9e9d323025
-Should be ifdef, since this is a global. You will never be doing and not an asic at the same time!
37 lines
1.1 KiB
Verilog
37 lines
1.1 KiB
Verilog
//#############################################################################
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//# Function: Clock mux #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_clockmux #(parameter N = 1) // number of clock inputs
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(
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input [N-1:0] en, // one hot enable vector (needs to be stable!)
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input [N-1:0] clkin,// one hot clock inputs (only one is active!)
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output clkout
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);
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`ifdef CFG_ASIC
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generate
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if((N==2))
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begin : asic
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asic_clockmux2 imux (.clkin(clkin[N-1:0]),
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.en(en[N-1:0]),
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.clkout(clkout));
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end
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else if((N==4))
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begin : asic
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asic_clockmux4 imux (.clkin(clkin[N-1:0]),
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.en(en[N-1:0]),
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.clkout(clkout));
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end
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endgenerate
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`else // !`ifdef CFG_ASIC
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assign clkout = |(clkin[N-1:0] & en[N-1:0]);
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`endif
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endmodule // oh_clockmux
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