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9e9d323025
-Should be ifdef, since this is a global. You will never be doing and not an asic at the same time!
85 lines
2.6 KiB
Verilog
85 lines
2.6 KiB
Verilog
//#############################################################################
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//# Function: Single Port Memory #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_memory_sp # (parameter DW = 104, // memory width
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parameter DEPTH = 32, // memory depth
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parameter MCW = 8, // repair/config width
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parameter AW = $clog2(DEPTH) // address bus width
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)
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(// memory interface (single port)
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input clk, // clock
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input en, // memory access
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input we, // write enable global signal
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input [DW-1:0] wem, // write enable vector
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input [AW-1:0] addr, // address
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input [DW-1:0] din, // data input
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output [DW-1:0] dout, // data output
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// Power/repair (ASICs)
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input vss, // common ground
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input vdd, // periphery power rail
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input vddm, // sram array power rail
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input shutdown, // shutdown signal from always on domain
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input [MCW-1:0] memconfig, // generic memory config
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input [MCW-1:0] memrepair, // repair vector
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// BIST interface (ASICs)
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input bist_en, // bist enable
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input bist_we, // write enable global signal
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input [DW-1:0] bist_wem, // write enable vector
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input [AW-1:0] bist_addr, // address
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input [DW-1:0] bist_din // data input
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);
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`ifdef CFG_ASIC
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asic_sram_sp #(.DW(DW),
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.DEPTH(DEPTH),
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.MCW(MCW))
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macro (// Outputs
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.dout (dout[DW-1:0]),
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// Inputs
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.clk (clk),
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.en (en),
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.we (we),
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.wem (wem[DW-1:0]),
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.addr (addr[AW-1:0]),
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.din (din[DW-1:0]),
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.vdd (vdd),
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.vddm (vddm),
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.vss (vss),
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.shutdown (shutdown),
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.memconfig (memconfig[MCW-1:0]),
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.memrepair (memrepair[MCW-1:0]),
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.bist_en (bist_en),
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.bist_we (bist_we),
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.bist_wem (bist_wem[DW-1:0]),
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.bist_addr (bist_addr[AW-1:0]),
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.bist_din (bist_din[DW-1:0]));
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`else // !`ifdef CFG_ASIC
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oh_memory_ram #(.DW(DW),
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.DEPTH(DEPTH))
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macro (//read port
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.rd_dout (dout[DW-1:0]),
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.rd_clk (clk),
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.rd_addr (addr[AW-1:0]),
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.rd_en (en & ~we),
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//write port
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.wr_clk (clk),
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.wr_en (en & we),
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.wr_addr (addr[AW-1:0]),
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.wr_wem (wem[DW-1:0]),
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.wr_din (din[DW-1:0]));
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`endif
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endmodule // oh_memory_sp
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