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oh/common/hdl/oh_pwr_isolo.v
Andreas.Olofsson 9e9d323025 Changing the CFG_ASIC approach
-Should be ifdef, since this is a global. You will never be doing and not an asic at the same time!
2020-02-04 23:04:52 -05:00

25 lines
914 B
Verilog

//#############################################################################
//# Function: Isolation (Low) buffer for multi supply domains #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_pwr_isolo #(parameter DW = 1 // width of data inputs
)
(
input iso,// active low isolation signal
input [DW-1:0] in, // input signal
output [DW-1:0] out // out = ~iso & in
);
`ifdef CFG_ASIC
asic_iso_lo iiso [DW-1:0] (.iso(iso),
.in(in[DW-1:0]),
.out(out[DW-1:0]));
`else
assign out[DW-1:0] = {(DW){~iso}} & in[DW-1:0];
`endif
endmodule // oh_buf