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https://github.com/aolofsson/oh.git
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290 lines
9.4 KiB
Verilog
290 lines
9.4 KiB
Verilog
module elink_example(/*AUTOARG*/
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// Outputs
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rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n, chipid, resetb, cclk_p, cclk_n,
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// Inputs
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reset, sys_clk_p, sys_clk_n, clkin_p, clkin_n, start, rxi_lclk_p,
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rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n,
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txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104; //packet width
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parameter ELINK_ID = 12'h810;
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parameter CHIP_ID = 12'h808;
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/****************************/
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/*CLOCKS AND RESET */
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/****************************/
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input reset; // active high async reset
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input sys_clk_p; // system input clock
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input sys_clk_n; // system input clock
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input clkin_p; // directly from pin
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input clkin_n; // directly from pin
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input start; // start generator
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/********************************/
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/*ELINK I/O PINS */
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/********************************/
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//Receiver
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input rxi_lclk_p, rxi_lclk_n; //link rx clock input
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input rxi_frame_p, rxi_frame_n; //link rx frame signal
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input [7:0] rxi_data_p, rxi_data_n; //link rx data
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output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
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output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
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//Transmitter
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output txo_lclk_p, txo_lclk_n; //link tx clock output
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output txo_frame_p, txo_frame_n; //link tx frame signal
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output [7:0] txo_data_p, txo_data_n; //link tx data
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input txi_wr_wait_p,txi_wr_wait_n; //link tx write pushback input
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input txi_rd_wait_p,txi_rd_wait_n; //link tx read pushback input
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/********************************/
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/*EPIPHANY INTERFACE (I/O PINS) */
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/********************************/
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output [11:0] chipid; // From etx of etx.v
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output resetb; //chip reset for Epiphany (active low)
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output cclk_p, cclk_n; //high speed clock (up to 1GHz) to Epiphany
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire done; // From egen_txwr of egen.v
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wire rx_clk_pll; // From elink of elink.v
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wire rx_lclk; // From eclocks of eclocks.v
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wire rx_lclk_div4; // From eclocks of eclocks.v
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wire soft_reset; // From elink of elink.v
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wire tx_lclk; // From eclocks of eclocks.v
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wire tx_lclk90; // From eclocks of eclocks.v
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wire tx_lclk_div4; // From eclocks of eclocks.v
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wire txrd_access; // From egen_txrd of egen.v
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wire [PW-1:0] txrd_packet; // From egen_txrd of egen.v
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wire txrd_wait; // From elink of elink.v
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wire txrr_access; // From emem of ememory.v
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wire [PW-1:0] txrr_packet; // From emem of ememory.v
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wire txrr_wait; // From elink of elink.v
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wire txwr_access; // From egen_txwr of egen.v
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wire [PW-1:0] txwr_packet; // From egen_txwr of egen.v
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wire txwr_wait; // From elink of elink.v
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// End of automatics
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//local wires
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wire pll_clk; // To eclocks of eclocks.v
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wire emem_access;
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wire [PW-1:0] emem_packet;
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wire rxrd_wait; // To elink of elink.v
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wire rxwr_wait; // To elink of elink.v
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wire rxrd_access; // From elink of elink.v
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wire [PW-1:0] rxrd_packet; // From elink of elink.v
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wire rxwr_access; // From elink of elink.v
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wire [PW-1:0] rxwr_packet; // From elink of elink.v
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wire rxrr_access; // From elink of elink.v
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wire [PW-1:0] rxrr_packet; // From elink of elink.v
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wire clkin;
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wire sys_clk_io;
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wire sys_clk;
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//PLL CLOCK INPUT
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IBUFGDS clk_buf1 (
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.I (clkin_p),
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.IB (clkin_n),
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.O (clkin)
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);
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BUFG bufg_pll (.I (clkin),
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.O (pll_clk)
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);
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//SYSTEM CLOCK INPUT
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IBUFGDS clk_buf3 (
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.I (sys_clk_p),
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.IB (sys_clk_n),
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.O (sys_clk_io)
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);
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BUFG bufg_sys (.I (sys_clk_io),
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.O (sys_clk)
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);
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//######
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//CLOCKS
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//######
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eclocks eclocks (
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.clkin_elink (rx_clk_pll),
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.clkin_cclk (pll_clk),
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/*AUTOINST*/
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// Outputs
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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// Inputs
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.reset (reset));
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//######
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//ELINK
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//######
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elink elink (.rxrr_wait (1'b0),
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.rxrr_access (rxrr_access),
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.mailbox_not_empty (),
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.mailbox_full (),
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.timeout (),
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.chipid (),
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.ioreset (reset),
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/*AUTOINST*/
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// Outputs
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.rx_clk_pll (rx_clk_pll),
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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.rxo_rd_wait_n (rxo_rd_wait_n),
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.txo_lclk_p (txo_lclk_p),
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.txo_lclk_n (txo_lclk_n),
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.txo_frame_p (txo_frame_p),
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.soft_reset (soft_reset),
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.txwr_wait (txwr_wait),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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// Inputs
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.reset (reset),
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.sys_clk (sys_clk),
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.tx_lclk (tx_lclk),
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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.rxi_frame_n (rxi_frame_n),
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.rxi_data_p (rxi_data_p[7:0]),
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.rxi_data_n (rxi_data_n[7:0]),
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.txi_wr_wait_p (txi_wr_wait_p),
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.txi_wr_wait_n (txi_wr_wait_n),
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.txi_rd_wait_p (txi_rd_wait_p),
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.txi_rd_wait_n (txi_rd_wait_n),
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.rxwr_wait (rxwr_wait),
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.rxrd_wait (rxrd_wait),
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.txwr_access (txwr_access),
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_access (txrd_access),
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.txrd_packet (txrd_packet[PW-1:0]),
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]));
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//############################
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//EMESH TRANSACTION GENERATOR
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//############################
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/*egen AUTO_TEMPLATE (
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// Outputs
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.\(.*\)_out (@"(substring vl-cell-name 5 9)"_\1[]),
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.\(.*\)_in (@"(substring vl-cell-name 5 9)"_\1[]),
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);
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*/
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defparam egen_txwr.MODE =1;//write
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defparam egen_txwr.SRC_ID=12'h810;
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defparam egen_txwr.DST_ID=12'h808;
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egen egen_txwr (.clk (sys_clk),
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/*AUTOINST*/
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// Outputs
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.done (done),
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.access_out (txwr_access), // Templated
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.packet_out (txwr_packet[PW-1:0]), // Templated
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// Inputs
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.reset (reset),
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.start (start),
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.wait_in (txwr_wait)); // Templated
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defparam egen_txrd.MODE=0;//read
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defparam egen_txrd.SRC_ID=12'h810;
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defparam egen_txrd.DST_ID=12'h808;
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egen egen_txrd ( .start (done),
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.done (),
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.clk (sys_clk),
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/*AUTOINST*/
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// Outputs
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.access_out (txrd_access), // Templated
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.packet_out (txrd_packet[PW-1:0]), // Templated
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// Inputs
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.reset (reset),
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.wait_in (txrd_wait)); // Templated
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//#################
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//EMESH MEMORY
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//##################
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assign emem_access = (rxwr_access & ~(rxwr_packet[39:28]==ELINK_ID)) |
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(rxrd_access & ~(rxrd_packet[39:28]==ELINK_ID));
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assign emem_packet[PW-1:0] = rxwr_access ? rxwr_packet[PW-1:0]:
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rxrd_packet[PW-1:0];
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assign rxrd_wait = emem_wait | rxwr_access;
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assign rxwr_wait = 1'b0; //no wait on write
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/*ememory AUTO_TEMPLATE (
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// Outputs
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.\(.*\)_out (txrr_\1[]),
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.\(.*\)_in (emem_\1[]),
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.wait_out (emem_wait),
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.wait_in (txrr_wait),
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.clk (sys_clk),
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);
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*/
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ememory emem (.wait_out (emem_wait),
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/*AUTOINST*/
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// Outputs
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.access_out (txrr_access), // Templated
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.packet_out (txrr_packet[PW-1:0]), // Templated
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// Inputs
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.clk (sys_clk), // Templated
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.reset (reset),
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.access_in (emem_access), // Templated
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.packet_in (emem_packet[PW-1:0]), // Templated
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.wait_in (txrr_wait)); // Templated
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endmodule // dv_elink
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../memory/hdl" "../../emesh/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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