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69 lines
2.1 KiB
Verilog
69 lines
2.1 KiB
Verilog
/*
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########################################################################
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EPIPHANY eLink RX Protocol block
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########################################################################
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This block takes the parallel output of the input deserializers, locates
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valid frame transitions, and decodes the bytes into standard eMesh
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protocol (104-bit transactions).
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*/
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module erx_protocol (/*AUTOARG*/
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// Outputs
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erx_access, erx_packet, remap_bypass,
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// Inputs
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reset, rx_enable, clk, rx_packet, rx_burst, rx_access
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter ID = 0;
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// System reset input
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input reset;
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input rx_enable;//Enables receiver
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// Parallel interface, 8 eLink bytes at a time
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input clk;
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input [PW-1:0] rx_packet;
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input rx_burst;
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input rx_access;
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// Output to MMU / filter
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output erx_access;
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output [PW-1:0] erx_packet;
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output remap_bypass; //needed for remapping logic
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assign erx_access = rx_access;
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assign erx_packet[PW-1:0] = rx_packet[PW-1:0];
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endmodule // erx_protocol
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// Local Variables:
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// verilog-library-directories:("." "../../common/hdl")
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// End:
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/*
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This file is part of the Parallella Project.
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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