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124 lines
3.5 KiB
Verilog
124 lines
3.5 KiB
Verilog
`timescale 1ns/1ps
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module dv_top();
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//static variables
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parameter PW = 104;
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parameter N = 1;
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parameter IDW = 12;
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//local variables
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integer r;
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wire [IDW-1:0] dv_coreid;
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wire [N*N-1:0] vdd;
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wire vss;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire clk; // From dv_ctrl of dv_ctrl.v
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wire [N-1:0] dut_access; // From dut of dut.v
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wire dut_active; // From dut of dut.v
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wire [N*PW-1:0] dut_packet; // From dut of dut.v
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wire [N-1:0] dut_wait; // From dut of dut.v
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wire nreset; // From dv_ctrl of dv_ctrl.v
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wire start; // From dv_ctrl of dv_ctrl.v
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wire [N-1:0] stim_access; // From dv_driver of dv_driver.v
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wire stim_done; // From dv_driver of dv_driver.v
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wire [N*PW-1:0] stim_packet; // From dv_driver of dv_driver.v
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wire [N-1:0] stim_wait; // From dv_driver of dv_driver.v
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// End of automatics
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/*AUTOINPUT*/
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/*AUTOUTPUT*/
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//####################################################
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//COREID
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//####################################################
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assign dv_coreid[IDW-1:0] = 12'h000;
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//############################################################
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// SIMULATION CONTROL
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// -reset & clok generation
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// -dumps stimulus
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//############################################################
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dv_ctrl dv_ctrl (.test_done (1'b1), //optimize later
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/*AUTOINST*/
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// Outputs
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.nreset (nreset),
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.clk (clk),
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.start (start),
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// Inputs
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.dut_active (dut_active),
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.stim_done (stim_done));
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//#############################################################
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// DEVICE UNDER TEST
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// -create your own module named dut to include at compile time
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//#############################################################
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/*dut AUTO_TEMPLATE(
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.\(.*\)_out (dut_\1[]),
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.\(.*\)_in (stim_\1[]),
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.clk (clk),
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);
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*/
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dut #(.PW(PW),
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.N(N)
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)
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dut (/*AUTOINST*/
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// Outputs
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.dut_active (dut_active),
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.access_out (dut_access[N-1:0]), // Templated
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.packet_out (dut_packet[N*PW-1:0]), // Templated
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.wait_out (dut_wait[N-1:0]), // Templated
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// Inputs
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.clk (clk), // Templated
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.nreset (nreset),
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.vdd (vdd[N*N-1:0]),
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.vss (vss),
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.access_in (stim_access[N-1:0]), // Templated
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.packet_in (stim_packet[N*PW-1:0]), // Templated
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.wait_in (stim_wait[N-1:0])); // Templated
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//##############################
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//# STIMULUS + MONITORS
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//##############################
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/*dv_driver AUTO_TEMPLATE(
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.name (@"(substring vl-cell-name 0 2)"_name[]),
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.coreid (@"(substring vl-cell-name 0 2)"_coreid[IDW-1:0]),
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.clk (clk),
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.reset (reset),
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);
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*/
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dv_driver #(.PW(PW),
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.N(N),
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.NAME("test"),
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.IDW(IDW)
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)
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dv_driver (.coreid (dv_coreid[IDW-1:0]),
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/*AUTOINST*/
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// Outputs
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.stim_access (stim_access[N-1:0]),
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.stim_packet (stim_packet[N*PW-1:0]),
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.stim_wait (stim_wait[N-1:0]),
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.stim_done (stim_done),
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// Inputs
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.clk (clk), // Templated
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.nreset (nreset),
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.start (start),
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.dut_access (dut_access[N-1:0]),
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.dut_packet (dut_packet[N*PW-1:0]),
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.dut_wait (dut_wait[N-1:0]));
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endmodule // dv_top
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../dv" "../../common/dv" )
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// End:
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