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4b384be602
- duh error - making output positive edge aligned, the negedge nastyness should be maintained within module...
53 lines
1.2 KiB
Verilog
53 lines
1.2 KiB
Verilog
/* Detects the common aligned positive edge for a
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* slow/fast clocks. The circuit uses the negedge of the fast clock
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* to sample the slow clock. Output is positive edge sampled.
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*
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* NOTE: Assumes clocks are aligned and synchronous!
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*
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* ___________ ___________
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* __/ \___________/ \ SLOWCLK
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* __ __ __ __ __ __
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* _/ \__/ \__/ \__/ \__/ \__/ \__/ FASTCLK
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* ___________ _________
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* ___/ 1 1 \_0_____0____/ CLK45
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* ____________ ___
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* ______/ 1 1 \___0____0___/ CLK90
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*
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* ____ ______
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* \________________/ \________ FIRSTEDGE
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*
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*
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*
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*/
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module edgealign (/*AUTOARG*/
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// Outputs
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firstedge,
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// Inputs
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fastclk, slowclk
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);
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input fastclk;
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input slowclk;
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output firstedge;
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reg clk45;
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reg clk90;
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reg firstedge;
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always @ (negedge fastclk)
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clk45 <= slowclk;
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always @ (posedge fastclk)
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begin
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clk90 <= clk45;
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firstedge <= ~clk45 & clk90;
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end
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//TODO: parametrized based on 1/N ratios?
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endmodule // edgealign
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