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de63dfd907
-stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib
45 lines
1.5 KiB
Verilog
45 lines
1.5 KiB
Verilog
//#############################################################################
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//# Function: Clock synchronizer #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_dsync
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#(parameter SYNCPIPE = 2, // number of sync stages
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parameter DELAY = 0, // random delay
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parameter SYN = "TRUE", // true=synthesizable
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parameter TYPE = "DEFAULT" // scell type/size
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)
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(
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input clk, // clock
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input nreset, // clock
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input din, // input data
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output dout // synchronized data
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);
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generate
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if(SYN == "TRUE") begin
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reg [SYNCPIPE:0] sync_pipe;
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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sync_pipe[SYNCPIPE:0] <= 'b0;
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else
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sync_pipe[SYNCPIPE:0] <= {sync_pipe[SYNCPIPE-1:0],din};
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// drive randomize delay from testbench
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assign dout = (DELAY & sync_pipe[SYNCPIPE]) | //extra cycle
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(~DELAY & sync_pipe[SYNCPIPE-1]); //default
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end // block: reg
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else
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begin
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asic_dsync #(.TYPE(TYPE),
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.SYN(SYN),
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.SYNCPIPE(SYNCPIPE))
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asic_dsync (.clk(clk),
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.nreset(nreset),
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.din(din),
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.dout(dout));
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end
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endgenerate
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endmodule // oh_dsync
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