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de63dfd907
-stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib
52 lines
1.5 KiB
Verilog
52 lines
1.5 KiB
Verilog
//#############################################################################
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//# Function: 12:1 one hot mux #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_mux12
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#(parameter N = 1 ) // width of mux
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(
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input sel11,
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input sel10,
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input sel9,
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input sel8,
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input sel7,
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input sel6,
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input sel5,
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input sel4,
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input sel3,
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input sel2,
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input sel1,
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input sel0,
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input [N-1:0] in11,
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input [N-1:0] in10,
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input [N-1:0] in9,
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input [N-1:0] in8,
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input [N-1:0] in7,
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input [N-1:0] in6,
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input [N-1:0] in5,
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input [N-1:0] in4,
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input [N-1:0] in3,
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input [N-1:0] in2,
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input [N-1:0] in1,
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input [N-1:0] in0,
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output [N-1:0] out //selected data output
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);
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assign out[N-1:0] = ({(N){sel0}} & in0[N-1:0] |
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{(N){sel1}} & in1[N-1:0] |
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{(N){sel2}} & in2[N-1:0] |
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{(N){sel3}} & in3[N-1:0] |
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{(N){sel4}} & in4[N-1:0] |
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{(N){sel5}} & in5[N-1:0] |
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{(N){sel6}} & in6[N-1:0] |
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{(N){sel7}} & in7[N-1:0] |
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{(N){sel8}} & in8[N-1:0] |
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{(N){sel9}} & in9[N-1:0] |
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{(N){sel10}} & in10[N-1:0] |
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{(N){sel11}} & in11[N-1:0]);
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endmodule // oh_mux12
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