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de63dfd907
-stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib
46 lines
1.4 KiB
Verilog
46 lines
1.4 KiB
Verilog
//#############################################################################
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//# Function: Rising Edge Sampled Register #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_reg1
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#(parameter N = 1, // vector width
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parameter SYN = "TRUE", // synthesizable (or not)
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parameter TYPE = "DEFAULT" // scell type/size
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)
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( input nreset, //async active low reset
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input clk, // clk
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input en, // write enable
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input [N-1:0] in, // input data
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output [N-1:0] out // output data (stable/latched when clk=1)
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);
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//TODO: Implement all classes of flip-flops
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generate
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if(SYN == "TRUE") begin
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reg [N-1:0] out_reg;
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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out_reg[N-1:0] <= 'b0;
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else if(en)
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out_reg[N-1:0] <= in[N-1:0];
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assign out[N-1:0] = out_reg[N-1:0];
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end
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else begin
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genvar i;
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for (i=0;i<N;i=i+1) begin
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asic_reg1 #(.TYPE(TYPE))
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asic_reg1 (// Outputs
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.out (out[i]),
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.en (en),
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.in (in[i]));
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end
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end
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endgenerate
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endmodule
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