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de63dfd907
-stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib
77 lines
2.3 KiB
Verilog
77 lines
2.3 KiB
Verilog
//#############################################################################
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//# Function: Parametrized register file #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_regfile
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# (parameter REGS = 8, // number of registeres
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parameter RW = 16, // register width
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parameter RP = 5, // read ports
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parameter WP = 3, // write prots
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parameter RAW = $clog2(REGS)// (derived) rf addr width
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)
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(//Control inputs
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input clk,
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// Write Ports (concatenated)
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input [WP-1:0] wr_valid, // write access
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input [WP*RAW-1:0] wr_addr, // register address
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input [WP*RW-1:0] wr_data, // write data
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// Read Ports (concatenated)
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input [RP-1:0] rd_valid, // read access
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input [RP*RAW-1:0] rd_addr, // register address
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output [RP*RW-1:0] rd_data // output data
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);
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reg [RW-1:0] mem[0:REGS-1];
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wire [WP-1:0] write_en [0:REGS-1];
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wire [RW-1:0] datamux [0:REGS-1];
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genvar i,j;
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//TODO: Make an array of cells
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//#########################################
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// write ports
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//#########################################
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//One hote write enables
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for(i=0;i<REGS;i=i+1)
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begin: gen_regwrite
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for(j=0;j<WP;j=j+1)
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begin: gen_wp
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assign write_en[i][j] = wr_valid[j] & (wr_addr[j*RAW+:RAW] == i);
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end
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end
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//Multi Write-Port Mux
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for(i=0;i<REGS;i=i+1)
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begin: gen_wrmux
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oh_mux #(.N(RW), .M(WP))
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iwrmux(.out (datamux[i][RW-1:0]),
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.sel (write_en[i][WP-1:0]),
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.in (wr_data[WP*RW-1:0]));
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end
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//Memory Array Write
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for(i=0;i<REGS;i=i+1)
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begin: gen_reg
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always @ (posedge clk)
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if (|write_en[i][WP-1:0])
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mem[i] <= datamux[i];
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end
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//#########################################
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// read ports
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//#########################################
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for (i=0;i<RP;i=i+1) begin: gen_rdport
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assign rd_data[i*RW+:RW] = {(RW){rd_valid[i]}} &
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mem[rd_addr[i*RAW+:RAW]];
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end
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endmodule // oh_regfile
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