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de63dfd907
-stdcells moved to asiclib, doesn't make sense to be vectorized -common is a stupid name, renamed as stdlib
27 lines
974 B
Verilog
27 lines
974 B
Verilog
//#############################################################################
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//# Function: Converts a rising edge to a single cycle pulse #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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//#############################################################################
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module oh_rise2pulse #(parameter N = 1) // data width
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( input clk, // clock
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input nreset, // async active low reset
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input [N-1:0] in, // edge input
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output [N-1:0] out // one cycle pulse
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);
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reg [N-1:0] in_reg;
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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in_reg[N-1:0] <= 'b0 ;
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else
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in_reg[N-1:0] <= in[N-1:0] ;
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assign out[N-1:0] = in[N-1:0] & ~in_reg[N-1:0] ;
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endmodule // oh_rise2pulse
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