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53 lines
1.7 KiB
Verilog
53 lines
1.7 KiB
Verilog
module packet2emesh(/*AUTOARG*/
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// Outputs
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write_out, datamode_out, ctrlmode_out, data_out, dstaddr_out,
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srcaddr_out,
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// Inputs
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packet_in
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);
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parameter PW = 104; //packet width
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parameter DW = 32; //data width
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parameter AW = 32; //addess width
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//Input packet
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input [PW-1:0] packet_in;
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//Emesh signal bundle
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output write_out;
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output [1:0] datamode_out;
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output [3:0] ctrlmode_out;
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output [DW-1:0] data_out; //TODO: fix to make relative to PW
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output [AW-1:0] dstaddr_out;
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output [AW-1:0] srcaddr_out;
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assign write_out = packet_in[0];
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assign datamode_out[1:0] = packet_in[2:1];
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assign ctrlmode_out[3:0] = packet_in[6:3];
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assign dstaddr_out[31:0] = packet_in[39:8];
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assign srcaddr_out[31:0] = packet_in[103:72];
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assign data_out[31:0] = packet_in[71:40];
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endmodule // packet2emesh
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/*
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Copyright (C) 2015 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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