Patrik Lindström 48fdf2d782 Added iostandard parameter

2015-06-30 12:44:22 +02:00

..

axi_elink.v

Added iostandard parameter

2015-06-30 12:44:22 +02:00

ecfg_elink.v

Name changes for signal grouping

2015-06-25 16:09:05 -04:00

ecfg_if.v

Adding filtering to ecfg_if

2015-05-19 23:52:00 -04:00

eclocks.v

Changed rx_ref_clk PLL divider

2015-06-30 12:35:38 +02:00

elink_constants.v

Using fifo_cdc instead of fifo_async

2015-05-07 23:45:36 -04:00

elink_regmap.v

MILESTONE: register read/write working!

2015-05-04 10:49:17 -04:00

elink.v

Name changes for signal grouping

2015-06-25 16:09:05 -04:00

emaxi.v

Fixing read response address

2015-05-20 15:04:29 -04:00

ereset.v

Synchronous exit from reset

2015-05-14 22:28:41 -04:00

erx_arbiter.v

Removing timeout from logic

2015-05-19 23:51:17 -04:00

erx_cfg.v

Converting to synchronous reset

2015-05-17 23:00:53 -04:00

erx_core.v

Integrating clock approach change

2015-05-13 23:29:18 -04:00

erx_fifo.v

Reset and clock cleanup

2015-05-14 22:31:42 -04:00

erx_io.v

MILESTONE: Bursts working!!!

2015-05-18 15:38:30 -04:00

erx_protocol.v

MILESTONE: Bursts working!!!

2015-05-18 15:38:30 -04:00

erx_remap.v

Converting to synchronous reset

2015-05-17 23:00:53 -04:00

erx_timer.v

Converting to synchronous reset

2015-05-17 23:00:53 -04:00

erx.v

Reset and clock cleanup

2015-05-14 22:31:42 -04:00

esaxi.v

Fixing read response address

2015-05-20 15:04:29 -04:00

etx_arbiter.v

Fixing read response address

2015-05-20 15:04:29 -04:00

etx_cfg.v

Converting to synchronous reset

2015-05-17 23:00:53 -04:00

etx_core.v

Integrating clock approach change

2015-05-13 23:29:18 -04:00

etx_fifo.v

Reset and clock cleanup

2015-05-14 22:31:42 -04:00

etx_io.v

MILESTONE: Bursts working!!!

2015-05-18 15:38:30 -04:00

etx_protocol.v

Letting read response packets through

2015-05-20 15:03:22 -04:00

etx_remap.v

Separate rd/wr stalls

2015-05-04 17:09:50 -04:00

etx.v

Reset and clock cleanup

2015-05-14 22:31:42 -04:00