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cdef6141b4
- Randomizeing clock frequencies - Phase and frequency randomization a must for catching first order sync problems (and debunking really stupid ideas...) - Don't be clever, be smart!
47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
// Standardized "DUT"
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module dut (/*AUTOARG*/
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// Outputs
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dut_active, clkout, access_out, packet_out, wait_out,
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// Inputs
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clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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parameter PW = 99;
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parameter N = 99;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk1;
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input clk2;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active; // dut ready to go after reset
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output clkout; // needed for monitor "source synchronous"
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//North side
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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input [N-1:0] wait_in;
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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output [N-1:0] wait_out;
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/*AUTOINPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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//Drive dummy interface
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//This module should be replaced with actual device under test
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assign access_out ='b0;
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assign packet_out ='b0;
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assign wait_out ='b0;
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endmodule // dut
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