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54 lines
1.3 KiB
Verilog
54 lines
1.3 KiB
Verilog
`include "spi_regmap.v"
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module spi_regs (/*AUTOARG*/
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// Outputs
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reg_rdata, cpol, cpha, txdata,
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// Inputs
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nreset, clk, reg_access, reg_packet, rxdata
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);
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//##################################################################
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//# INTERFACE
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//##################################################################
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parameter AW = 32; // data width of fifo
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parameter PW = 2*AW+40; // packet size
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parameter DEPTH = 32; // fifo depth
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//clk+reset
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input nreset; // asynchronous active low reset
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input clk; // write clock
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//register access
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input reg_access; // register access (read only)
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input [PW-1:0] reg_packet; // data/address
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output [31:0] reg_rdata; // readback data
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//controls
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output cpol;
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output cpha;
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//io interface
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output [7:0] txdata; // data in txfifo
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input [7:0] rxdata; // data for rxfifo
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//##################################################################
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//# BODY
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//##################################################################
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reg [31:0] status_reg;
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reg [31:0] config_reg;
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reg [31:0] ilat_reg;
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reg [31:0] imask_reg;
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reg [31:0] delay_reg;
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reg [31:0] tx_reg;
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reg [31:0] rx_reg;
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endmodule // spi_regs
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