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103 lines
2.7 KiB
Verilog
103 lines
2.7 KiB
Verilog
module dut(/*AUTOARG*/
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// Outputs
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dut_active, wait_out, access_out, packet_out,
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// Inputs
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clk, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2;
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parameter IDW = 12;
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parameter M_IDW = 6;
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parameter S_IDW = 12;
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parameter PW = 104;
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parameter N = 1;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transactoin
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire m_miso; // From spi of spi.v
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wire m_mosi; // From spi of spi.v
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wire m_sclk; // From spi of spi.v
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wire m_ss; // From spi of spi.v
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wire [31:0] reg_rdata; // From spi of spi.v
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wire spi_irq; // From spi of spi.v
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// End of automatics
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wire [AW-1:0] gpio_in; // To gpio of gpio.v
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reg [N-1:0] access_out;
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//######################################################################
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//DUT
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//######################################################################
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assign gpio_in[AW-1:0] = 32'h87654321;
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assign wait_out[N-1:0] = 'b0;
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assign dut_active = 1'b1;
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always @ (posedge clk)
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access_out[0] <= access_in[0] & ~packet_in[0];
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emesh2packet e2p (// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.write_out (1'b0),
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.datamode_out (2'b10),
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.ctrlmode_out (5'b0),
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.dstaddr_out ({(AW){1'b0}}),
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.data_out (reg_rdata[AW-1:0]),
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.srcaddr_out ({(AW){1'b0}})
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);
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/*spi AUTO_TEMPLATE(.s_\(.*\) (m_\1),
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);
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*/
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spi spi (.reg_access (access_in[0]),
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.reg_packet (packet_in[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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.reg_rdata (reg_rdata[31:0]),
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.spi_irq (spi_irq),
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.m_sclk (m_sclk),
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.m_mosi (m_mosi),
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.m_ss (m_ss),
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.s_miso (m_miso), // Templated
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.m_miso (m_miso),
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.s_sclk (m_sclk), // Templated
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.s_mosi (m_mosi), // Templated
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.s_ss (m_ss)); // Templated
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endmodule // dut
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
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// End:
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