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-Each directory contains one sub block -Each directory contains a dv/docs/hdl directory, self contained. -May need to add constraints directory as well at some point. -This is the right thing to do, make each block modular and self contained.
59 lines
1.3 KiB
Verilog
59 lines
1.3 KiB
Verilog
/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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module pulse2toggle(/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, in, reset
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);
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//clocks
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input clk;
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input in;
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output out;
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//reset
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input reset;
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reg out;
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wire toggle;
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//if input goes high, toggle output
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//note1: input can only be high for one clock cycle
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//note2: be careful with clock gating
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assign toggle = in ? ~out :
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out;
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always @ (posedge clk or posedge reset)
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if(reset)
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out <= 1'b0;
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else
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out <= toggle;
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endmodule // pulse2toggle
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