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-Each directory contains one sub block -Each directory contains a dv/docs/hdl directory, self contained. -May need to add constraints directory as well at some point. -This is the right thing to do, make each block modular and self contained.
229 lines
8.8 KiB
Verilog
229 lines
8.8 KiB
Verilog
/*
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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/*########################################################################
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AXI WRAPPER FOR ECFG BLOCK
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########################################################################
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*/
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module axi_ecfg (/*AUTOARG*/
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// Outputs
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s_axi_awready, s_axi_wready, s_axi_bresp, s_axi_bvalid,
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s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid,
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esys_tx_enable, esys_tx_mmu_mode, esys_tx_gpio_mode,
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esys_tx_ctrl_mode, esys_tx_clkdiv, esys_rx_enable,
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esys_rx_mmu_mode, esys_rx_gpio_mode, esys_rx_loopback_mode,
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esys_cclk_div, esys_cclk_pllcfg, esys_coreid, esys_dataout,
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esys_irqsrc_read,
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// Inputs
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s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awprot,
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s_axi_awvalid, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
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s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
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s_axi_rready, param_coreid, erx_irq_fifo_src, erx_irq_fifo_data,
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erx_rdfifo_access, erx_rdfifo_wait, erx_wrfifo_access,
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erx_wrfifo_wait, erx_wbfifo_access, erx_wbfifo_wait,
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etx_rdfifo_access, etx_rdfifo_wait, etx_wrfifo_access,
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etx_wrfifo_wait, etx_wbfifo_access, etx_wbfifo_wait
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);
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//Register file parameters
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/*
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#####################################################################
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COMPILE TIME PARAMETERS
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######################################################################
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*/
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parameter DW = 32; //elink monitor register width
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parameter AW = 32; //mmu table address width
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parameter SW = DW/8; //mmu table address width
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parameter MAW = 6; //register file address width
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parameter MDW = 32; //
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parameter IDW = 12; //Elink ID (row,column coordinate)
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/*****************************/
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/*AXI SLAVE INTERFACE (LITE) */
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/*****************************/
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//Global signals
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input s_axi_aclk; //clock source for axi slave interfaces
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input s_axi_aresetn; //asynchronous reset signal, active low
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//Write address channel
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input [AW-1:0] s_axi_awaddr; //write address
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input [2:0] s_axi_awprot; //write protection type
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input s_axi_awvalid; //write address valid
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output s_axi_awready; //write address ready
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//Write data channel
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input [DW-1:0] s_axi_wdata; //write data
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input [SW-1:0] s_axi_wstrb; //write strobes
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input s_axi_wvalid; //write valid
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output s_axi_wready; //write channel ready
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//Buffered write response channel
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input s_axi_bready; //write ready
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output [1:0] s_axi_bresp; //write response
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output s_axi_bvalid; //write response valid
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//Read address channel
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input [AW-1:0] s_axi_araddr; //read address
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input [2:0] s_axi_arprot; //read protection type
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input s_axi_arvalid; //read address valid
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output s_axi_arready; //read address ready
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//Read data channel
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output [DW-1:0] s_axi_rdata; //read data
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output [1:0] s_axi_rresp; //read response
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output s_axi_rvalid; //read valid
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input s_axi_rready; //read ready
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/*****************************/
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/*STATIC SIGNALS */
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/*****************************/
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input [IDW-1:0] param_coreid;
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/*****************************/
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/*ELINK DATAPATH INPUTS */
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/*****************************/
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input [11:0] erx_irq_fifo_src;
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input [11:0] erx_irq_fifo_data;
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input erx_rdfifo_access;
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input erx_rdfifo_wait;
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input erx_wrfifo_access;
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input erx_wrfifo_wait;
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input erx_wbfifo_access;
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input erx_wbfifo_wait;
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input etx_rdfifo_access;
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input etx_rdfifo_wait;
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input etx_wrfifo_access;
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input etx_wrfifo_wait;
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input etx_wbfifo_access;
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input etx_wbfifo_wait;
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/*****************************/
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/*ECFG CONTROL OUTPUTS */
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/*****************************/
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//tx
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output esys_tx_enable; //enable signal for TX
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output esys_tx_mmu_mode; //enables MMU on transnmit path
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output esys_tx_gpio_mode; //forces TX output pins to constants
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output [3:0] esys_tx_ctrl_mode; //value for emesh ctrlmode tag
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output [3:0] esys_tx_clkdiv; //transmit clock divider
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//rx
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output esys_rx_enable; //enable signal for rx
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output esys_rx_mmu_mode; //enables MMU on rx path
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output esys_rx_gpio_mode; //forces rx wait pins to constants
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output esys_rx_loopback_mode; //loops back tx to rx receiver (after serdes)
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//cclk
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output [3:0] esys_cclk_div; //cclk divider setting
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output [3:0] esys_cclk_pllcfg; //pll configuration
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//coreid
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output [11:0] esys_coreid; //core-id for fpga elink
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//gpio
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output [11:0] esys_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0}
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//irq
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output esys_irqsrc_read; //increments the irq fifo pointer
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] ecfg_cclk_div; // From ecfg of ecfg.v
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wire [3:0] ecfg_cclk_pllcfg; // From ecfg of ecfg.v
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wire [11:0] ecfg_coreid; // From ecfg of ecfg.v
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wire [11:0] ecfg_dataout; // From ecfg of ecfg.v
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wire ecfg_rx_enable; // From ecfg of ecfg.v
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wire ecfg_rx_gpio_mode; // From ecfg of ecfg.v
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wire ecfg_rx_loopback_mode; // From ecfg of ecfg.v
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wire ecfg_rx_mmu_mode; // From ecfg of ecfg.v
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wire [3:0] ecfg_tx_clkdiv; // From ecfg of ecfg.v
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wire [3:0] ecfg_tx_ctrl_mode; // From ecfg of ecfg.v
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wire ecfg_tx_enable; // From ecfg of ecfg.v
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wire ecfg_tx_gpio_mode; // From ecfg of ecfg.v
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wire ecfg_tx_mmu_mode; // From ecfg of ecfg.v
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wire mi_access; // From axi_memif of axi_memif.v
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wire [MAW-1:0] mi_addr; // From axi_memif of axi_memif.v
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wire [MDW-1:0] mi_data_in; // From axi_memif of axi_memif.v
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wire [31:0] mi_data_out; // From ecfg of ecfg.v
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wire mi_write; // From axi_memif of axi_memif.v
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// End of automatics
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axi_memif axi_memif(/*AUTOINST*/
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// Outputs
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.s_axi_awready (s_axi_awready),
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.s_axi_wready (s_axi_wready),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_arready (s_axi_arready),
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.s_axi_rdata (s_axi_rdata[DW-1:0]),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rvalid (s_axi_rvalid),
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.mi_addr (mi_addr[MAW-1:0]),
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.mi_access (mi_access),
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.mi_write (mi_write),
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.mi_data_in (mi_data_in[MDW-1:0]),
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// Inputs
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awaddr (s_axi_awaddr[AW-1:0]),
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.s_axi_awprot (s_axi_awprot[2:0]),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_wdata (s_axi_wdata[DW-1:0]),
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.s_axi_wstrb (s_axi_wstrb[SW-1:0]),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_bready (s_axi_bready),
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.s_axi_araddr (s_axi_araddr[AW-1:0]),
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.s_axi_arprot (s_axi_arprot[2:0]),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_rready (s_axi_rready),
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.mi_data_out (mi_data_out[MDW-1:0]));
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ecfg ecfg(
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/*AUTOINST*/
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// Outputs
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.mi_data_out (mi_data_out[31:0]),
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.ecfg_tx_enable (ecfg_tx_enable),
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.ecfg_tx_mmu_mode (ecfg_tx_mmu_mode),
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.ecfg_tx_gpio_mode (ecfg_tx_gpio_mode),
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.ecfg_tx_ctrl_mode (ecfg_tx_ctrl_mode[3:0]),
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.ecfg_tx_clkdiv (ecfg_tx_clkdiv[3:0]),
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.ecfg_rx_enable (ecfg_rx_enable),
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.ecfg_rx_mmu_mode (ecfg_rx_mmu_mode),
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.ecfg_rx_gpio_mode (ecfg_rx_gpio_mode),
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.ecfg_rx_loopback_mode (ecfg_rx_loopback_mode),
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.ecfg_cclk_div (ecfg_cclk_div[3:0]),
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.ecfg_cclk_pllcfg (ecfg_cclk_pllcfg[3:0]),
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.ecfg_coreid (ecfg_coreid[11:0]),
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.ecfg_dataout (ecfg_dataout[11:0]),
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// Inputs
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.param_coreid (param_coreid[IDW-1:0]),
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.clk (clk),
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.reset (reset),
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.mi_access (mi_access),
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.mi_write (mi_write),
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.mi_addr (mi_addr[5:0]),
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.mi_data_in (mi_data_in[31:0]));
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endmodule // axi_ecfg
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// Local Variables:
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// verilog-library-directories:("." "../axi")
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// End:
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