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289024fd89
- Creating an arbitrary 'src' directory really doesn't help much... - Goal is to make each folder self contained - Make meta repos and individual repos have the same directory structure
45 lines
1.6 KiB
Verilog
45 lines
1.6 KiB
Verilog
/*############################################################################
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* PROGRAMMABLE DELAY ELEMENT
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*
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* NOTE: NOT AVAILABLE IN HR BANKS!
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*
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*############################################################################
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*/
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module ODELAYE2 (/*AUTOARG*/
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// Outputs
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CNTVALUEOUT, DATAOUT,
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// Inputs
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C, CE, CINVCTRL, CLKIN, CNTVALUEIN, INC, LD, LDPIPEEN, ODATAIN,
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REGRST
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);
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parameter CINVCTRL_SEL = "FALSE";
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parameter DELAY_SRC = "ODATAIN";
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parameter HIGH_PERFORMANCE_MODE = "FALSE";
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_ODATAIN_INVERTED = 1'b0;
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parameter ODELAY_TYPE = "FIXED";
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parameter integer ODELAY_VALUE = 0;
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parameter PIPE_SEL = "FALSE";
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parameter real REFCLK_FREQUENCY = 200.0;
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parameter SIGNAL_PATTERN = "DATA";
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input C; //clock for VARIABLE, VAR_LOAD,VAR_LOAD_PIPE mode
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input REGRST; //reset pipeline reg to all zeroes
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input LD; //loads programmed values depending on "mode"
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input CE; //enable encrement/decrement function
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input INC; //increment/decrement tap delays
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input CINVCTRL; //dynamically inverts clock polarity
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input [4:0] CNTVALUEIN; //input value from FPGA logic
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input CLKIN; //clk from I/O clock mux??
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input ODATAIN; //data from OSERDESE2 output
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output DATAOUT; //delayed data to pin
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input LDPIPEEN; //enables pipeline reg??
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output [4:0] CNTVALUEOUT; //current value for FPGA logic
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assign DATAOUT=ODATAIN;
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endmodule // ODELAYE2
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