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25 lines
459 B
Verilog
25 lines
459 B
Verilog
module oh_abs (/*AUTOARG*/
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// Outputs
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out, overflow,
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// Inputs
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in
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);
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parameter DW = 4;
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//inputs
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input [DW-1:0] in; //input operand
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//outputs
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output [DW-1:0] out; //out = abs(in) (signed two's complement)
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output overflow; //high for max negative #
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assign out[DW-1:0] = in[DW-1] ? ~in[DW-1:0] + 1'b1 :
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in[DW-1:0];
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assign overflow = in[DW-1] & ~(|in[DW-2:0]);
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endmodule // oh_abs
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